Custom Design Flow– Basic to Advanced

In a typical design environment, one or two key Lead designers (Design Lead, Integration Lead, EDA Lead etc.) control the overall design environment and the rest of the team follows the set up as a default. One important requirements to become the Lead is that you need not only to be the master on one area (e.g.- RTL design, Circuit design, Integration), rather you need to have the overall understanding of entire Methodology (Key components- Tools/ PDKs/ Standard Cell/ Technology files/ Config. file/ Debugging/ Version control etc. and the Flow- Input-output at each phase of the design, Tool interactions) for the design environment (Become the Go to person for the group/ company). This module will use a typical "custom design process" (schematic to parasitic simulation) as a reference flow, but the focus of the training will be to make you a power user with the overall design methodology.

Currently Scheduled Course Dates

• Jan 26, 2011 - Dallas, TX

What you’ll learn from this course

• How to become an expert with custom design flow
• How to get the best out of EDA tools and PDKs
• What are the most efficient ways of debugging
• Sample automation of entire custom flow

Course Prerequisite

• Basic understandings of Custom design flow

Overview of the course

• Steps/ Components for a Custom design flow
  • Schematic
  • Schematic simulation
  • Layout generation (Manual vs. Automated)
  • Physical Verification (DRC, LVS, DFM, Methodology)
  • Parasitic Extraction
  • Parasitic Simulation
• Control/ Initialization files- Get the best out of EDA tools
• Technology files/ PDKs
  • CDK
  • Model
  • DRC deck
  • LVS deck
  • PEX deck
  • Customizing the decks
• Efficient debugging- Tips and Tricks
• Advanced topics of Custom Design Methodology

Sample slides

• Few sample slides from the course content.

Who Should Attend

• Analog designer
• Physical designer
• Layout designer
• Digital designer
• ASIC designer
• EDA/Methodology/ Flow Engineers
• EEs from small design companies/startup, responsible for several phases of the design.
• New college graduates (BS, MS or PhD- EE/CS)

Course Materials

• A hardcopy of the "Presentation materials" will be included as part of the course.

Instructor's Profile: Faizul Alam

Faizul Alam is the CTO and Co-Founder of CatalyteIC, a leading provider of “IC Design/Methodology” and “High-end IC Design Training” Services. He has 15+ years of experience with various aspects of Physical Design (PD) – Process Design Kit (PDK) / Physical Verification (PV) infrastructure development, Parasitic Extraction, Tools, Methodologies and Implementations. Faizul worked for TI between 2004 and 2009, leading the PDK developments at advanced process nodes (Deck quality, QC automation, iPDK, DFM etc. for 65 nm, 45 nm and 28 nm technology). Prior to TI, Faizul worked for IBM as “Custom Physical Design Methodology" Lead- responsible for the tools, infra-structure and verification for “Cell” Processor, for STI (Sony-Toshiba-IBM) design center.

Faizul published/presented 10+ papers in major conferences including ICCAD, CDNLive and ACEED. He holds two Master’s degree (ECE and EEE) from University of Florida and Bangladesh University of Engineering and Technology (BUET), respectively. He is a senior member of IEEE.