Design and Verification with SystemC

"Design and Verification with SystemC" provides a comprehensive introduction to the powerful modeling capabilities of the SystemC language using a rich set of examples and techniques used with SystemC. SystemC is a naturally object-oriented language that allows designers to use familiar hardware concepts such as modules and interfaces to model their design at high and intermediate levels of abstraction. A gentle introduction to the object-oriented programming paradigm is provided using the C++ language. We then get attendees up to speed with SystemC programming concepts such as data types, modules and hierarchies, processes and time, interfaces and channels, adapters, bus modeling, and transaction-level modeling using Open Source SystemC Simulator. All of this is geared to enable smooth transition to design and verification with SystemC. We also provide an overview of available software tools that work with SystemC to aid design and verification process.

Jan 18, 2011 - Dallas, TX
Jan 25, 2011 - Dallas, TX

Introduction to power management techniques
Gets you up to speed with System C language, RTL and Transaction-Level
Hands-on experience with Open Source SystemC Simulator on some concepts.
Includes design and verification situations to stimulate in-depth knowledge of the language

Basic understanding of digital design and verification is the only pre-requisite for this course.
Knowledge of one of the hardware description languages such as Verilog, VHDL, or SystemVerilog
C/C++ knowledge is helpful but not required.

Overview of SystemC
- C++ background for System
- Introduction to SystemC RTL
- Modeling Synchronous Logic with SystemC
- Writing Testbenches with SystemC
- Introduction to the SystemC Simulator
  1. Setting up SystemC Simulator
  2. Creating a small arithmetic module
  3. Simulating arithmetic module for validation
Modeling Beyond RTL
- Processes in SystemC
- Ports, Interfaces, and Channels
- Notion of Time and Concurrency
- Basic Channels and Interfaces
- Packet-based Verification in Networking
  1. Packet Generation
  2. Driving Packets to Ports
  3. Error Injection
Transaction-Level Modeling (TLM) Methodology
- Abstraction models
- TLM-Based Methodology
- An Introduction to TLM2

Few sample slides from the course content.

All digital design engineers (design and verification) and design managers involved in designing chips for various electronic markets.

System-level design engineers
Digital module design engineers
System-level design engineers
Digital module design engineers
Embedded design and verification engineers
Managers of design and verification engineers
EE/CS Graduate Students planning to work in the semiconductor industry

A hardcopy of the "Presentation materials" will be included as part of the course.

Dr. Bhanu Kapoor is the founder, president, and owner at Mimasic, a consulting services company in the area of digital low power design and verification. He started his career with Texas Instruments where he played various technical roles (1987-99) at TI’s DSP R&D Center. He has played leading technology development roles in EDA startups ArchPro (now Synopsys), Atrenta, and Verisity (now Cadence). He is an expert in the area of low power design and verification. He is the lead inventor on 6 US patents in the area of low power design and verification and has over 40 publications in various IEEE/ACM conferences and journals. Bhanu graduated from the Indian Institute of Technology (IITK) in 1987 with a degree in Electrical Engineering. He has received M.S. (1990) and Ph.D. (1994) degrees in Computer Science from SMU, Dallas. He is also an adjunct professor of Computer Science and Electrical Engineering at SMU, Dallas and served as Vice President (Outside of India) of IITK Alumni Association.