Introduction to system verilog for designers and verification engineers

Introduction to system verilog for designers and verification engineers

System Verilog, the newest revision of the IEEE standard Verilog hardware description language, provides a number of features that are useful for RTL designers and verification engineers. This training module covers synthesizable features of System Verilog as well as some verification focused features. These features can boost productivity by enabling the use of higher-level abstractions and facilitating more easily understood code. This training module is not a simply a language course. Rather, this module focuses on real-world coding examples that help to motivate the use of the language features.

Currently Scheduled Course Dates

  • Jan 26, 2011 - Austin, TX
  • Jan 28, 2011 - Dallas, TX

What you’ll learn from this course

This workshop will enable engineers who use Verilog to immediately be productive modeling complex hardware designs using the SystemVerilog extensions to the Verilog language. You’ll learn

  • What the most useful System Verilog extensions are
  • How and when to incorporate new modeling techniques into your designs
  • How to leverage System Verilog covergroups to facilitate coverage measurement.
  • How to create simple assertions to check interface assumptions and to enable white box checking of your designs

Course Prerequisite

  • Basic understandings of RTL Design and Verification.

Overview of the course

  • Introduction to System Verilog
    • Purpose
    • Synthesis subset
    • Verification extensions
  • Design hierarchy
    • Package declaration and use
    • Nested modules
    • Enhanced port connection syntax
  • Data types
    • New data types
    • Enumerated types
    • Arrays
    • Structs
  • Data types
    • Integer and logic literals
    • Struct and array literals
  • Procedural blocks
    • Sequential and combinational procedural blocks
    • Why are these important
    • Task and function enhancements
    • Reference arguments
  • Programming statements and operators
    • New operators
    • Enhanced looping constructs
    • Unique and priority decision statements
  • System Verilog Interfaces
    • Interface definition
    • Defining module ports and directions
    • Using interfaces
  • Assertions
    • Assertion concepts
    • Concurrent assertions and sequences
    • Basic sequence definitions
    • Disabling assertions during reset
    • Assertion messages
  • Coverage
    • Coverage concepts
    • System Verilog coverage statements
    • Cover coverage versus functional coverage
  • Wrap-up
    • What was not covered
    • Exploring further

Sample slides

Who Should Attend

This module assumes the attendee has a basic level of knowledge of Verilog and only covers System Verilog enhancements to Verilog. A variety of engineers could benefit including

  • Digital designers looking to upgrade their skill set
  • ASIC designers looking to understand how System Verilog features can positively impact their designs
  • EDA Methodology / Flow engineers who want to understand how adopting System Verilog can enhance their methodology.
  • Engineers from startups or smaller design companies who are responsible for several phases of work.
  • Verification engineers who want to understand System Verilog hardware modeling extensions or who want to influence the direction of RTL design to higher abstraction levels.

Course Materials

  • A hardcopy of the "Presentation materials" will be included as part of the course.

Instructor's Profile: Paul Hylander

Paul Hylander is an expert in the design and verification of integrated circuits and has over 15 years of experience in leading companies such as HP and Cadence Design Systems as well as several cutting-edge startups. At HP, he provided technical direction to a team of engineers to develop state-of-the-art microprocessors and ASICs for HP high-end computers. As an architect during his tenure at Cadence Design Systems, Paul was responsible for one of Cadence’s industry-leading verification tools. In addition, Paul was responsible for working with top-tier customers such as Intel and Texas Instruments.

Paul was a founder of Nucleus Logic, where he held the CTO position and was responsible for the architecture, and initial implementation of their core-logic integrated networking ASICs. Prior to Nucleus Logic, Paul was with Archway Digital Solutions, where he was the verification lead for a Gigabit TCP/IP offload ASIC and was the architect for the 10Gigabit generation.

Presently, Paul is the Founder and CEO of Hyper Analytix, a verification tools and services company. There he consults on verification projects for leading IC designs. In addition, he is the lead architect and developer for a new generation of verification tools.

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