SoC Power Management Design and Verification

Power is a primary design criterion for bulk of the semiconductor designs now and a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past. Voltage and Clock are two of the strongest handles for managing chip power consumption. We look into the details of some of the key power management techniques that leverage voltage and clock as a handle and their impact on chip verification; these include Multiple Clock Domains, Clock Gating, Power Gating, Power Gating with Retention, Multiple Supply Voltages, Dynamic Voltage Scaling, Adaptive Voltage Scaling, Multi-Threshold CMOS, and Active Body Bias. The use these techniques imply new challenges in validation of designs as new power states are created. We dive into details of several new verification issues that can potentially lead to a re-spin and are a direct result of using these techniques. These issues have been seen while working with chips used in cell phones and other hand-held devices; they pose a real threat to any low power design in various application areas that plan to use these techniques.

Jan 26, 2011 - Dallas, TX
Jan 24, 2011 - Austin, TX

Introduction to power management techniques
Discuss verification issues due to the use of these techniques
Details of implementing power management techniques
Details of handling verification issues arising due to power management techniques
Hands-on experience with verification issues in real design situations via a set of exercises and quizzes

Basic understanding of digital design and verification is the only pre-requisite for this course.

Power Management Fundamentals
- System’s perspective on power becoming a fundamental concern
- Dynamic Power
- Leakage Power and its impacts on 65nm & beyond
- SoC Power Management Techniques
- Impact of Power Management Techniques on Dynamic and Leakage Power
Power Management Architecture Design Implications
- Power Gating and Retention Implications
- Multi-voltage Implications
- Power Management ICs (PMIC) Fundamentals
- Design of Controller logic in conjunction with PMICs
  1. Isolation, Retention, and Level-shifter Controls
- Case Studies of Power Managed Designs
  1. Renesas Processor
  2. TI OMAP 2320
Power Management Architecture Verification Implications
- Design verification implications of each power management technique
- Isolation, Retention, and Level-shifter verification
  1. Simulation
  2. Formal Techniques
  3. Rule-based Techniques
- Emerging power format standard [UPF/IEEE p1801 and CPF]
- Case Studies for Verification
  1. A 3-islands design with independent power on/off capabilities
  2. Renesas Processor
  3. TI OMAP 2320
- Tools and Methodology Implications
  1. Tools for Verification
  2. Tools for Implementation
  3. Gaps in design needs and tool availability
- Topic-based Hands-on exercises/quizzes to validate understanding of concepts

Few sample slides from the course content.

All digital design engineers (design and verification) and design managers involved in designing chips that are targeting application areas that are power sensitive. The construction of the training is motivated from design experience in cell phone processors, GPS for mobile devices, media and graphics processors for hand-held devices, single-core and multi-core general purpose processors targeting hand-held applications, and some power sensitive networking chips.

System-level design engineers
Digital module design engineers
Embedded design and verification engineers
Managers of design and verification engineers
EE/CS Graduate Students planning to work in the semiconductor industry

A hardcopy of the "Presentation materials" will be included as part of the course.

Dr. Bhanu Kapoor is the founder, president, and owner at Mimasic, a consulting services company in the area of digital low power design and verification. He started his career with Texas Instruments where he played various technical roles (1987-99) at TI’s DSP R&D Center. He has played leading technology development roles in EDA startups ArchPro (now Synopsys), Atrenta, and Verisity (now Cadence). He is an expert in the area of low power design and verification. He is the lead inventor on 6 US patents in the area of low power design and verification and has over 40 publications in various IEEE/ACM conferences and journals. Bhanu graduated from the Indian Institute of Technology (IITK) in 1987 with a degree in Electrical Engineering. He has received M.S. (1990) and Ph.D. (1994) degrees in Computer Science from SMU, Dallas. He is also an adjunct professor of Computer Science and Electrical Engineering at SMU, Dallas and served as Vice President (Outside of India) of IITK Alumni Association.